This invention relates to a semiconductor integrated circuits (ICs) of the type having output signal pad cell driver circuits connected to these output signal pads to control the rise and fall rates, or slew rates, of digital logic signals supplied by the IC. More particularly, the present invention relates to a new and improved output signal driver circuit which automatically selects among multiple delay circuits for changing the slew rate of the digital logic output signals to accommodate variable impedance loads connected to the output pad of the IC.
The switching or transition rate of an output signal, referred to as the slew rate, describes the rate at which the voltage of the output signal changes with respect to time (dv/dt). Ideally, the slew rate of the circuit would be infinitely high, causing the output signal to change from one logic state to the other logic state instantaneously. However, due to natural effects and energy storage of the components connected to the output pads of the IC, the logic state cannot change instantaneously. A greater the amount of time required for the output signal to transition from one logic state to the other logic state reduces the switching speed of the IC.
Modern ICs require high switching speeds, and higher switching speeds are made possible by more rapid slew rates. Maintaining high slew rates can be difficult because it is almost impossible to predict the type and amount of impedance or load which may be connected to the output pads of a commercially available IC, particularly any IC which is capable of use in many applications. For example, ICs used in signal communication applications must comply with the applicable communication specifications and protocols. Many of these protocols, such as small computer standard interface (SCSI) and the personal computer interface (PCI) bus interconnect standards, specify drive signal strength, signal delay time from input to output, and the slew rates of the output signal, among other things. It may be particularly difficult to meet these specifications under circumstances where the extent of the load which may be connected to the output pads of a communication IC varies substantially.
To attempt to maintain a high slew rate without regard to the amount of the natural and intended load connected to the output pad of the IC, it is typical that an output signal pad cell driver, such as a transistor or a group of transistors be fabricated as part of the IC to provide the additional energy needed to compensate for the natural output loading effects and to speed up or control the slew rate transition from one logic state to the other. However, if the driver transistors switch logic states too rapidly, the output digital signal may experience degradation problems caused by overshoot, undershoot, or ringing, which in turn, may produce false signals and malfunctions in the IC. Furthermore, if the drivers are switched on and off too quickly, voltage spikes, known as ground bounce, may propagate unwanted voltage transients throughout the IC. Such unwanted voltage transients may also cause aberrant operation.
One solution to the above mentioned problems is to slow the slew rate. However, a diminished slew rate runs counter to the intent of designing faster ICs having more rapid switching times. It is with regard to these and other considerations and problems that the present invention has evolved.
The present invention involves an output signal pad cell driver circuit of an IC which achieves an increased slew rate and switching speed, while avoiding signal degradation and other problems which may have been previously inherent in achieving increased slew rates and switching speeds. Another feature of the present invention involves sensing the slew rate of the output signal according to the amount of loading or impedance connected to the output signal pad of the IC and adjusting that slew rate based on the initial slew rate to achieve a predetermined slew rate which is more independent of the impedance or loading connected to the output pad. A further feature of the present invention involves selecting and applying multiple different time delay circuit driving capabilities which maintain a predetermined slew rate even under circumstances where different impedances or loads are connected to the output pad. A further feature of the present invention involves selecting and applying multiple different circuit driving capabilities to control the slew rate according to whether the output signal transitions from a logic low to a logic high state in one case or whether the output signal transitions from a logic high to a logic low state in the other case.
To achieve these and other features, an output signal pad cell driver circuit of the present invention controls the slew rate of a digital logic output signal delivered from an output pad of an integrated circuit relative to a load connected to the output pad. The output signal occurs in response to an input digital logic signal. The driver circuit comprises a first timing circuit, a second timing circuit and a switching circuit. The first timing circuit generates a plurality of first trigger signals which occur at sequentially spaced time intervals with respect to one another. The second timing circuit generates a plurality of second trigger signals which occur at sequentially spaced time intervals with respect to one another and at time intervals different from the time intervals of the first trigger signals. One of the timing circuits responds to the input signal to initiate the generation of its plurality of trigger signals, and the other timing circuit responds to the output signal as influenced by the load connected to the output pad to initiate the generation its plurality of trigger signals. The switching circuit includes a plurality of drive switches connected to the output pad and responsive to the pluralities of the first and second trigger signals, with the control signals controlling the conductivity of the drive switches to establish the slew rate of the output signal.
The previously mentioned in other features of the present invention are also achieved by a method of controlling the slew rate of a digital logic output signal delivered from an output pad of an integrated circuit relative to a load connected to the output pad, in response to the occurrence of an input digital logic signal. The method comprises steps including generating a plurality of first trigger signals at sequentially spaced time intervals with respect to one another, in response to the occurrence of the input signal; generating a plurality of second trigger signals at sequentially spaced time intervals with respect to one another and at time intervals different from the time intervals of the first trigger signals; adjusting at least one of the time intervals between the first and second trigger signals or the temporal occurrence of the first and second trigger signals in relation to the load connected to the output pad; selecting one of the pluralities of the first and second signals; and changing the level of the output signal at the output pad in relation to the occurrence of the selected one plurality of second signals by changing the conductivity of a conductivity element connected to the output pad in relation to each trigger signal.
Other preferred aspects of the output signal pad cell driver circuit and the method of controlling the slew rate include circuit elements and method steps, respectively, which permit generating the first ones of the pluralities of the first and second trigger signals at different times, responding to a change in the output signal to deliver one plurality of trigger signals while responding to a change in the input signal to initiate delivery of the other plurality of trigger signals, controlling the application of trigger signals to the drive switches in relation to one of a transition of the input signal from a logic low state to a logic high state or a transition of the input signal from a logic high state to a logic low state, delaying for a predetermined time after the occurrence of the input signal before generating one of the pluralities of trigger signals, and counting a predetermined time after the occurrence of the input signal at which to select the one of the pluralities of trigger signals.
A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, by reference to the following detailed description of presently preferred embodiments of the invention, and by reference to the appended claims.